IF AN ELECTRONIC DEVICE is to be a major commercial success, it has to deliver great performance at an affordable price.
Judged in these terms, GaN-on-silicon technology is very promising. HEMTs formed with this material system have many great attributes − including a high mobility, a high critical field and a high current density − and they can be produced at relatively low cost, thanks to manufacture in mature silicon processing lines.
One perceived weakness with this class of device is that its performance is held back by the large mismatches in the lattice constant and the coefficient of thermal expansion between GaN and silicon (111). However, tremendous progress in epitaxial technology over the past few years has addressed these concerns, and today AlGaN/GaN-on-silicon HEMTs compete in performance with cousins made on SiC. Thanks to their performance parity with GaN-on-SiC, there is a good chance that HEMTs made on silicon could see insertion into high-fidelity applications, such as airborne radar in the L-band to X-band regime.
GaN-on-silicon devices that can be used for power and RF switching are thermally limited. This restriction actually affects all semiconductor devices, but with GaN-on-silicon the impact is particularly significant because of their aforementioned electrical performance advantages. Consequently, the downsides of a higher device operating temperature are not limited to a lower gain and efficiency, but also include reliability concerns.
These reliability-related issues stem from the structure of the device. Although advances in GaN-on-silicon technology have enabled the production of very high quality, low-dislocation density GaN buffer layers, realising a high-quality heterostructure requires thick, highly defective AlGaN and/or AlN nucleation layers on the substrate side (see Figure 1).
Figure 1. Transmission-electron microscope image of a GaN-on-silicon wafer cross section.
These layers, combined with a relatively thick SiN passivation on the device side, create a GaN-on-silicon HEMT that is optimized for electrical performance, but has an electrothermal performance that is impaired by a low thermal conductivity for the nucleation and passivation layers (see Table I). For the nucleation layers, the thermal conductivity diminishes near the silicon substrate, due to the increase in defect density. Another issue is the use of ternary nucleation layers, such as AlGaN – this has a lower thermal conductivity than its binary constituents, AlN and GaN.
Table I. Thermal Properties of Relevant Device Materials
To improve the electrical performance of the GaN-on-silicon HEMT several groups have pioneered approaches associated with substrate-side engineering. This includes Farid Medjdoub’s group at IEMN that has increased the breakdown voltage of the device through localized removal of the silicon substrate beneath the transistor (see, for example, Compound Semiconductor Nov&Dec p. 58 (2015)), and the team led by Prof. Tomás Palacios at the Massachusetts Institute of Technology that have delivered a hike in breakdown voltage by switching from a silicon substrate to one made with quartz.
At the Naval Research Laboratory in Washington DC we are taking a holistic approach to improving the performance of the HEMT. We are not limiting our efforts to optimising electrical performance, but also aiming to build a device that delivers its best, in terms of its thermal and mechanical characteristics. We believe that the silicon substrate is an essential ingredient for the ultimate success of the GaN-based HEMT, and we are investigating whether improvements can be wrought from removing the substrate and accessing the nucleation layers, which might ultimately be replaced with effective, substrate-side, electrothermal passivation.
We are not alone in exploring the possible benefits of substrate removal. Palacios’ team at MIT have carried out dry plasma etching of silicon beneath the AlGaN/GaN heterostructure, and they found an increase in the carrier density of the two-dimensional electron gas following substrate thinning from 500 µm to 350 µm. Further etching was detrimental, however, with cracks in the GaN epistructure and reduced electrical performance occurring for devices with silicon substrates thinned to 150 µm.
The origin of the epiwafer cracks is not clear to us. High-power plasma etching causes wafers to heat up, and cracks might stem from the additional stress induced by heating, or by etching – or even by a combination of the two. As we are keen to know if our device process is limited by the lattice or thermal mismatch of GaN and silicon, we have investigated the impact of substrate thinning processes on device performance.
Efforts began by studying the consequences of substrate thinning on the characteristics of AlGaN/GaN-on-silicon HEMTs. MOCVD-grown 4-inch epiwafers with 575 & μm-thick (111) silicon substrates were thinned to 200 μm and 150 μm at room temperature by backgrinding and chemical mechanical polishing.
We evaluated the strain in these epiwafers with wafer curvature interferometry and Raman spectroscopy. Strain increased with processing, being inversely proportional to final substrate thickness. However, sheet resistance was nearly unchanged, prompting us to fabricate devices from our thinned epiwafers (see Figure 2 for maps of sheet resistance).
Figure 2. Thinning the silicon substrate from 575 µm to 200 µm (a) and 150 µm (b) did not produce any significant change in the sheet resistance profile.
The characteristics of the material degraded after ohmic contact annealing. Sheet resistance shot up by more than 150 percent, according to transfer length measurements (see Table II), and shallow cracks appeared on the surface of the AlGaN barrier (Figure 3). The cause of all of this degradation is the high-temperature contact anneal, which relaxed the stress that built-up in the heterostructure by partial substrate removal. Transistors formed from these thinned epiwafers suffered from a low drain current density and a fall in channel electron density – it is about a third of its original value, based on Hall measurements. This particular investigation highlights the thermal fragility of AlGaN/GaN heterostructures, which can be compromised by the large difference between the coefficient of thermal expansion of GaN and that of silicon.
Figure 3. Atomic force microscope images of the AlGaN surface of a sample from wafer B (a) before and (b) after an 850 °C, 30 s anneal in N2 atmosphere. Each image covers a 5 μm x 5 μm surface area.
Two options for avoiding the hike in sheet resistance caused by rapid-thermal annealing are to carry out ohmic contact deposition prior to substrate thinning, and to employ a non-alloyed ohmic metallization process. We would like to go one better, however, and do away with the silicon substrate altogether.
Table 2. Comparison of AlGaN/GaN HEMTs as a function of substrate thickness and high temperature annealing.
Success will hinge on developing a process that can remove all of the silicon without damaging the heterostructure, and without introducing additional thermal boundaries in the device. Our plan is that after removing the silicon substrate, having temporarily attached our epistructure to a thermally-matched carrier wafer, we will deposit on our III-Ns, at a high temperature, a thick, high-thermal-conductivity layer of diamond.
We believe that replacing the silicon substrate with a high thermal conductivity material, such as diamond, will aid the production of GaN transistors delivering optimal electrothermal performance. The ultimate improvement in electrothermal performance, however, will not result from just removing the silicon substrate – it will require a stripping away of all the low thermal conductivity layers in the heterostructure. This is a challenge for us and other developers of GaN HEMTs, with success requiring new device processes and novel HEMT architectures.